The present invention reelates to methods of manufacturing integrated circuits.
As the dimensions of microcircuit elements continue to decrease, the ability to control the etched sidewall profiles of contact holes or vias (particularly in the size range of 0.8 to 1.25 microns, and below) becomes increasingly difficult, and also increasingly critical. Of even more importance is the coverage of sidewalls with deposited metal. Traditionally the contacts have been sloped by reflowing doped oxide, but this method has serious disadvantages: it can seriously degrade contact resistance in CMOS circuits, and for small contact holes the size of the opening is difficult to control. Although substantial efforts (with some success) have been devoted to lowering the temperatures required for reflow, reflow methods are inherently high temperature steps.
One common method used to slope contact holes is the resist erosion (resist etchback) technique. With this method the resist is patterned with 50 to 60 degree slopes. This is followed with a plasma oxide etch with a high resist etch rate, which serves to transfer the resist slope into the oxide and then a plasma overetch with selectivity to underlying silicon to yield slopes in the range of 60 to 70 degrees. The principal problem with this method is the difficulty in controlling the resist slope, especially at sizes close to 1.0 micron. Resist loss greater than 0.7 micron is necessary to transfer the slope into the silicon oxide, which can cause oxide failures where the resist thins over steps. Also, the contact hole enlarges during the overetch, typically by 0.3 to 0.4 microns. This problem is discussed in Saia and Gorowitz, Dry Etching of Tapered Contact Holes Using Multilayer Resist, 132 J. ELECTROCHEMICAL SOCIETY: SOLID-STATE SCIENCE AND TECHNOLOGY p. 1954 (1985), which is hereby incorporated by reference.
One known technique which has provided some success is the use of a cantilever mask to obtain sloped sidewalls. The technique involves elevating the mask above the substrate with an undercut spacer layer. Such a structure allows etching to occur under the elevated mask. Due to the properties of the ions as they bombard the oxide surface, as the distance the ions travel increases there is a continuing decrease of the etch rate thereby generating nicely contoured wall profiles. See Rothman, Mauer, Schwartz, and Logan, Process for Forming Tapered Vias in SiO.sub.2 by Reactive Ion Etching, in PROCEEDINGS OF THE SYMPOSIUM ON PLASMA ETCHING AND DEPOSITION, 193 (1982), which is hereby incorporated by reference; and Reynolds, Hollins, and Neureuther, Studies of Plasma Etching Mechanisms with Cantilever Structures, in PROCEEDINGS OF THE SYMPOSIUM ON PLASMA ETCHING AND DEPOSITION, Electrochemical Society, 61 (1983), which is hereby incorporated by reference.
The usual method of generating the cantilever structure is the use of a trilayer resist scheme. With this method standard photoresist is used to mask a hard inorganic layer over a spacer of thick photoresist hardbaked at 180.degree. C. or greater. The hardened photoresist is undercut (from under the patterned hardmask layer) with a dry etch, and the oxide is etched to produce the sloped contacts desired. However, this method has substantial drawbacks, namely the complication of the added etch and deposition steps, the difficulty inspecting alignment through the several layers, and the difficulty in removing the hard mask after etch of the contact. See Bonifield, Douglas, Huffman, and Dennington, Sloped Contact Etching, in TEGAL: PLASMA SEMINAR PROCEEDINGS (1985), which is hereby incorporated by reference; and Bonifield and Douglas, Cantilevered Masks for Sloped Sidewalls on Plasma Etched Dielectrics, in IEEE Lithography Workshop (1984), which is hereby incorporated by reference.
The present invention provides a much simpler and more manufacturable method of producing cantilever etch masks using a simple modification of a multilayer resist scheme, the sestertius resist process.
The sestertius cantilever mask approach requires no extra etch or deposition steps, only the coating and developing of conventional lithographic materials; alignment is easy to inspect, and the stack is removed easily with standard resist stripping techniques.
The sestertius resist process is a modification of the Portable Conformable Mask technique in which a anti-reflective coating layer is applied between the photoresist and the PMMA to control standing waves and reflective notching in the top layer and prevent the formation of interfacial scum due to intermixing between the PMAA and the photoresist. See the paper by Lin in SPIE volume 174 (1979), which is hereby incorporated by reference. The sestertius process may be thought of as a "two and one-half" layer process, since the anti-reflective coating is coated in a separate step, but is etched during the development of the imaging layer. See Lin, Jones, and Fuller, Use of Anti-reflective Coating in Bilayer Resist Processes, JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY B1, (1983), which is hereby incorporated by reference, and Lin, Marriott, Orvek, and Fuller, Some Aspects of Anti-reflective Coating for Optical Lithography, in SPIE VOLUME 469, ADVANCES IN RESIST TECHNOLOGY (1984), which is hereby incorporated by reference.
In the present invention, the cantilever structure is very conveniently obtained by overexposing and overdeveloping the PMMA, which is a non-critical step.
That is, the method of the present invention not only provides additional advantages over the sestertius method, but is also more manufacturable. The pattern transfer step, wherein the developed pattern in the top layer is exposed to transfer it into the spacer layer, was a tricky step in the sestertius process, but in the present invention this step is not critical at all, since very large overexposure and overdevelopment margins are used.
Thus, the present invention provides at least the following advantages, in addition to others mentioned in this application:
it requires only a one step etch which is selective to silicon. PA0 the slope of the contact is determined primarily by the cantilevered mask spacer thickness. PA0 the sizing of the contact is determined by the size of the printed contact in the top imaging layer. PA0 the sestertius resist is removed in a standard resist strip process. PA0 it uses a high resolution multilayer resist process. PA0 the etch profile has naturally rounded corners.